M.Senthil Sivakumar, BE(ECE), M.Tech (VLSI Design)
Best Research Project Awards:
“CADENCE
DESIGN india CONTEST 2009”, Bangalore, India.
Project: Design of Dynamically
Reconfigurable Fully Optimized Low Power FFT/IFFT Architecture for MC-CDMA
Receiver.
“INTEL INDIA SCHOLARSHIP PROGRAM 2008”, Bangalore, India.
Project: Low Power CMOS Dynamic Logic for Arithmetic Circuits
With High Speed.
WORKING EXPERIENCE:
1.Assistant Professor at NIT
Puducherry, Karaikal, India – January 2014 to Till date
2.Lecturer at St. Joseph University in Tanzania, East Africa – Sept 2009
to Oct 2013.
Responsibilities: Providing quality
Lectures and Subject material, Preparing 3 set of Question paper/answer key
preparation, Question verification/error rectification, Paper valuation, Guiding
innovative projects, IPTR visit & validation and Curriculum review.
3.Lecturer at Gojan School of Business
and technology, Chennai, India - 2005 to 2007
Responsibilities: Providing quality
Lectures and Subject material, Paper valuation, Guiding innovative projects and
validation.
PublicationS:
TEXT BOOKS:-
1.
Book for “Fundamentals of DIGITAL DESIGN”-Printing progress.
2.
Book for “Linear Integrated circuit” -Published by
S.Chand publishers, ISBN: 978-81-219-4113-6. http://www.schandgroup.com/book_cd_details.asp?Cd=10545&BC=B&isEbook=False
RESEARCH PAPERS:
Conference:
Pan-African
Conference for Information Science, Computing and Telecommunications (PACT) -
July 2013, Lusaka, Zambia conducted by La
Trobe University Australia, University of Zambia and IEEE region 8. (IEEE
Proceedings)
Titles:
1. Senthil
Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Banupriya M, “4-Bit
Manchester Carry Look-Ahead Adder Design Using MT-CMOS Domino Logic”, PACT’13,
pp.15-18.
2. Senthil
Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Banupriya M, “Design of
Adaptive MC-CDMA receiver using low power parallel-pipelined FFT architecture”,
PACT’13, pp.29-33.
3. Arputharaj T, Senthil
Sivakumar M, Arockia Jayadhas S, and Banupriya M, “Design of Low Noise Active
Integrated Antenna”, PACT’13, pp.66-69.
4. Senthil
Sivakumar M, Banupriya M, Jaykishan Murji, Lightness D Jacob, and Frank Nyange,
“Speech Controlled Automatic Wheelchair”, PACT’13, pp.70-73.
International
Conference on Electrical Sciences (ICES - 2012), September 14th-15th,
2012, Paper ID: ICES 055.
Title: Senthil
Sivakumar M, Arivu Selvam, and Banupriya M, “Design of 4-Bit Carry Look-Ahead
Adder Using MT-CMOS Dynamic Logic” ICES 2012, page-42.
International
Conference on Active /Smart Materials
(ICASM), 2009, Madurai, India.
Titles:
1.
M.Senthil Sivakumar, Jhonson G, “Fast Adders Using
High performance low power CMOS dynamic logic” ICASM 2009.
2.
M.Senthil Sivakumar, Rakesh Kumar, and L.Thanga
Durai, “High performance Carbon Nano Tube (CNT)-Field Effect Transistor”, ICASM
2009.
Journals:
1.
Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T,
and Banupriya M “Design of 4-Bit Manchester Carry Look-Ahead Adder Using
MT-CMOS Domino Logic”, African Journal of Information and Communication
Technology (AJICT) 2013 – Publication Progress.
2.
Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T,
and Banupriya M “Design of Dynamically Reconfigurable Adaptive MC-CDMA Receiver
using FFT Architecture”, African Journal of Information and Communication
Technology (AJICT) 2013, Vol.7, No.2, pp.49-61.
3.
Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T,
and Banupriya M, “Low Noise Active Integrated Antenna for S-Band”, African
Journal of Information and Communication Technology (AJICT) 2013, Vol.7, No.2,
2013, pp.37-48.
4.
Senthil Sivakumar M, Banupriya M, Arockia Jayadhas S,
Arputharaj T, “Speech Controlled Automatic Wheelchair for Home Navigation
System”, International Journal of Machine to Machine Communication (JMMC),
River Publishers Denmark– Publication Progress.
5. Senthil Sivakumar M, Arockia Jayadhas
S, Arputharaj T, and Ramkumar E, “Design of MT-CMOS Domino Logic for Ultra Low
Power High Performance Ripple Carry Adder”, IJESC, vol.5, No.1, Jan-Jun, 2013,
pp.37-40.
6. Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T,
and Ramkumar E, “Design of
MT-CMOS Domino Logic for Ultra Low Power High Performance Ripple Carry Adder”, International Journal of Emerging Trends
in Engineering and Development (IJETED), Jan 2013, vol.1, issue 3, pp.574-579.
7.
Senthil Sivakumar M, Banupriya M, “Low power high
performance design consideration of CMOS domino logic for fast adders”, Journal
of Scientific Theory and Methods, 2012, vol.12, pp.22-39.
8.
Senthil Sivakumar M, Banupriya M, Arockia Jayadhas S, “Design
of Low Power High Performance 16-Point 2-Parallel Pipelined FFT Architecture”, IJECIERD, Sept 2012, vol.2, issue.3,
pp.12-26. http://tjprc.org/download.php?fname=--1346685923-2.%20Electronics%20-%20IJECEIERD%20-%20Design%20of%20Low%20-%20Senthil%20Sivakumar%20-%20Paid.pdf
9.
Senthil Sivakumar M, Banupriya M, “Design Consideration
of Dual Threshold Logic for High Performance and Ultralow Power Carry
Look-Ahead Adder”, IJSER, vol.3, issue 6, June 2012, pp. 1301-1306. http://www.ijser.org/viewPaperDetail.aspx?I015675
10. Senthil
Sivakumar M, Banupriya M, “High Speed Low Power Flash ADC Design for Ultra Wide
Band Applications”, IJSER, vol.3, issue 5, May 2012, pp.389-393. http://www.ijser.org/viewPaperDetail.aspx?I014577
Reviewed papers:
1.
G.Narmadha, K.Balasubadra,
SACS M.AV.M.M Engg.College, Design Of Time Efficient Carry Select Adder Using
FPGA”, International Journal of Electronics, 2013.
2.
Choi, GoangSeog,
Shanmugam, Muthukumar, Chosun University, ‘Power and Area-Optimized Carry
Select Adder Architecture for Standard Cell-based Design’, International
Journal of Electronics, 2013.
3. K.Kunaraj, R.Seshasayanan, Anna
University, “Leading one detectors and leading one position detectors – an
evolutionary design methodology”, International Journal of Electronics 2012.
